A preview of the papers appearing in the April 2006 issue of the Journal of the SID. To obtain access to these articles on-line, please go to www.sid.org

Edited by Aris Silzars

Integrated a-Si TFT row driver circuits for high-resolution applications

Cheon-Hong Kim
Se-Jong Yoo
Hyun-Jin Kim
Jung-Mok Jun
Jung-Yeal Lee

BOE-HYDIS Technology Co.

Abstract — A 12.1-in. tablet liquid-crystal-display (LCD) panel with integrated amorphous-silicon row driver circuits has been developed using a standard TFT process and Advanced Fringe-Field Switching (AFFS) technology. An XGA-resolution 768-stage shift-register circuit with two-phase clocks has been designed and fabricated. The circuit parameters were optimized in order to obtain a highly reliable a-Si row-driver-circuit structure. Thermal Humidity Operation (THO) test results at 50°C and 80% humidity during 500 hours of operation shows that the fabricated panel is reliable during long-term operation and any abnormal display phenomenon was not observed at 0°C.

There are several obstacles to the implementation of a-Si TFT backplanes with integrated row driver circuits. First, the low carrier mobility (~0.5 cm2/V-sec) of hydrogenated a-Si TFTs causes speed and area limitation of a-Si TFT integrated circuits. And the absence of a PMOS load makes circuit design more difficult because it is impossible to implement complementary circuit structure. Third, high and variable parasitic capacitance due to the non-self-aligned device structure causes signal distortion due to the clock feed-through. Finally, the instability of a-Si TFTs with time and temperature, that is, degradation of device characteristics with time and a decrease in ON-current at low temperature, induces long-term reliability at high temperature and device instability issues at low temperature.

FIGURE 7 — Low-temperature operation at 0°C.

A 510-kb SOG-DRAM for mobile displays with embedded frame memories

H. Haga, Y. Nonaka,
Y. Kamon, T. Otose,
D. Sasaki, Y. Kitagishi,
T. Matsuzaki, Y. Sato,
H. Asada

NEC LCD Technologies

Abstract — A system-on-glass (SOG) dynamic random access memory (DRAM), which enables the implementation of frame-memory-integrated displays, has been developed. A dynamic one-transistor-one-capacitor memory cell, which has a data retention time of over 16.6 msec and a compression/decompression (CODEC) circuit were developed to reduce the layout area and power. The CODEC enables an 18-bit/pixel color display, while reducing the memory capacity from 18 to 12 bits/pixel. A frame-memory macro was created by combining the SOG-DRAM with an embedded controller that enables independent access for writing and reading. Its operation was verified by chip measurement and demonstration as a frame-memory operation of 262k-color QCIF+ displays. The work reported in this paper was the first step to creating a Zero-Chip Display with an integrated frame memory, and it proved the concept was feasible.

SOG displays are eventually expected to lead to a Zero-Chip Display, which does not need external IC chips, by integrating the frame-memory, display controller, and CPU interface as shown in Fig. 1. It can be directly connected to master devices using common interface signals, such as addresses, data, and commands. Therefore, the Zero-Chip Display will have benefits of smaller volume and lighter weight, and it will cost less than current displays. In addition, it will lower the power consumption of mobile terminals because it enables static images to be continuously displayed without video data having to be transferred from the master devices. Moreover, it will shorten the lead times for the display module and for the mobile terminals.

FIGURE 1 — Concept of Zero-Chip display. It can be directly connected to a master device through common I/F signals without external IC chips. Integration of the frame memory onto the display panel is essential.

LTPS circuit integration for system-on-glass LCDs

Alex Ching-Wei Lin, Ting-Kuo Chang,
Chueh-Kuei Jan, Meng-Hsun Hsieh,
Chung-Yang Tsai
James Shih-Chang Chang
Alan Yaw-Ming Tsai

Toppoly Optoelectronics Corp.

Abstract — A 3.5-in. QVGA-formatted driving-circuit fully integrated LCD has been developed using low-temperature poly-Si (LTPS) technology. This display module, in which no external ICs are required, integrates all the driving circuits for a six-bit RGB digital interface with an LTPS device called a "FASt LDD TFT" and achieves a high-quality image, narrow frame width, and low power consumption. The LTPS process, device, and circuit technologies developed for system-on-glass LCD is discussed. The development phase of LTPS circuit integration for system-on-glass LCDs is also reviewed.

FIGURE 1 — The development phases of SOG-LCDs.

Compact and power-saving polysilicon data driver with common-decoder DA converter (CD-DAC)

Hiroshi Kageyama
Mitsuhide Miyamoto
Hajime Akimoto
Shigeyuki Nishitani
Toshihiro Sato
Toshio Miyazawa

Hitachi Control Research Laboratory

Abstract — A common-decoder architecture for a data-driver circuit fabricated by using a polysilicon process has been developed. The architecture achieves a compact circuit and low-power consumption. In application to an integrated polysilicon data driver for small-sized displays, this architecture reduces the area of the data driver by removing the vertical bus lines that occupy a large area. It also suppresses the power consumption of the data bus by reducing the number of driven lines in the data bus during word-to-word transitions from six to two. By using a conventional 4-μm design rule, an active-matrix OLED (AMOLED) panel with an integrated six-bit data-driver circuit with 384 outputs was fabricated. The driver circuit had a height of 2.6 mm and a pitch between output lines of 84 μm. The maximum power consumption of the driver was only 5 mW, i.e., 3.8 mW for logic-data transfer and 1.2 mW for reference-voltage source. Furthermore, an active-matrix LCD (AMLCD) panel, including driver circuits of the same type as the integrated elements, was also fabricated. Six-bit full-color images were successfully displayed on both panels.

To achieve a workable driver-circuit area with a conventional architecture, a process that allows a fine design rule, such as the 2-μm high-precision design rule, has to be used to fabricate the driver circuit. However, the need for extremely high precision in the fabrication of the driving circuit alone needed to be avoided. Thus, the difference in the number of interconnect layers possible with the LTPS and conventional LSI processes was noted. While three or even more layers are available with the LSI processes, only two layers, the SD metal layer and the gate metal layer, are available with the LTPS process. This is why the signal lines for the DACs take up such a large area in the conventional architecture. In this paper, a new architecture, called the common-decoder DAC, in which a single common decoder is used with the entire circuit-cell matrix, is proposed. This architecture achieves a compact and power-savings six-bit driver circuit, even with fabrication under a conventional 4-μm design rule.

FIGURE 1 — Architecture of the data-driver circuit. The proposed circuit does not need vertical data buses which occupy a large area in the conventional LTPS driver circuit.

Incorporation of input function into displays using LTPS TFT technology

T. Nakamura, H. Hayashi,
M. Yoshida, N. Tada,
M. Ishikawa, T. Motai,
H. Nakamura, T. Nishibe

Toshiba Matsushita Display Technology Co.

Abstract — A new display in which an input function is incorporated has been developed by using LTPS TFT technology. A new circuit configuration that includes a lateral p–i–n diode with an in-pixel amplifier, an LTPS A/D converter on the periphery of the glass substrate, and an external image-processing LSI is presented. The experimental results of two major applications of the image-capture function and touch-panel function are discussed.

FIGURE 10 — Color image capturing using the newly developed LCD.

10-bit source driver with resistor-resistor-string digital-to-analog converter

Yoo-Chang Sung
Oh-Kyong Kwon
Jong-Kee Kim

Hanyang University

Abstract — A 10-bit gray-scale source driver using a resistor-resistor-string digital-to-analog converter (RR-DAC) is proposed for a TFT-LCD source driver. The 10-bit RR-DAC consists of an 8-bit resistor-string DAC and a two-bit resistor-string DAC without an intermediate unity-gain buffer to isolate the parallel-connected resistor string. The output deviation of the proposed source driver is less than ±3 mV. The chip area of the proposed 10-bit source driver with an RR-DAC is increased to 29% of that of an 8-bit source driver.

The proposed RR-DAC is shown in Fig. 3. It consists of an 8-bit resistor-string DAC and a 2-bit resistor-string DAC without a unity-gain buffer. There are two global 8-bit resistor strings in the source driver for the polarity inversion of the liquid crystal. Each channel has an 8-bit decoder block, a 2-bit local resistor string, and a 2-bit decoder. An 8-bit decoder block selects two adjacent analog outputs and a local 2-bit resistor-string DAC divides the voltage between two adjacent analog outputs into four levels.

FIGURE 3 — Block diagram of proposed 10-bit resistor-resistor DAC.

A new driving method to compensate for row-line signal-propagation delays in an AMLCD

Soo Hwan Kim
Hyunwoo Park
Suki Kim
Richard McCartney

Korea University

Abstract — The row-line and data-line that make up of a TFT-LCD panel can be modeled as a distributed resistance and capacitance network. As TFT-LCD panels become larger and provide higher resolution, the induced signal propagation delay time from the row and column lines become an appreciable part of the line time. In particular, the row signal-propagation delay time is traditionally accommodated by waiting for the worst-case propagation time before the start of a new line. This conventional method, however, reduces the subpixel charging time. A new driving method, Horizontal Line Delay Compensation (H-LDC) has been implemented and verified to compensate for row-line propagation delay. The benefit of longer subpixel charging time is of particular interest to large-area high-resolution fast-refresh-rate LCD TVs.

Horizontal line delay compensation (H-LDC) is an alternate method to compensate for the propagation delay of the row signal. Rather than transitioning all the outputs of all the column drivers simultaneously, each output of each column driver is delayed an amount that matches the propagating edge of the row signal as it passes that output. In other words, each column-driver time staggers their output transitions, in step with the row-signal propagation, to assure that the column driver changes starts immediately after the row-signal falls. This means that since no output must wait for the gate signal to propagate, whether the column-driver output is near or far from the row driver, there is additional time to charge each pixel.

FIGURE 8 — Brightness pattern due to the propagation delay in the LCD panel. (OE signal is 2 μsec.)

Motion artifact elimination technology for liquid-crystal-display monitors: Advanced dynamic capacitance compensation method

Seung-Woo Lee
Myeongsu Kim
Jun H. Souk
Sang Soo Kim

Kyung Hee University

Abstract — A new technology, advanced dynamic capacitance compensation (A-DCC), for improved dynamic performance of LCD monitors, is presented. Conventional LCD monitors suffer from certain specific artifacts, such as wire-frame flicker and line dimming, which are not issues for the simpler motion images found in television content. A-DCC addresses these more-challenging monitor cases by means of an advanced architecture which analyzes multi-frame data and applies more comprehensive lookup-table corrections according to the specific frame sequence.

A-DCC is the latest overdrive technology. To minimize monitor-specific motion artifacts including wire-frame flickering and line dimming, conventional overdrive was applied. But, due to the limitations and additional artifacts, conventional overdrive is not sufficient. A-DCC improves rising transition characteristics and considers dynamic transitions in addition to static transitions. In addition, response symmetry is a key capability of A-DCC. Using these advanced capabilities, A-DCC can effectively eliminate monitor-specific motion artifacts.

FIGURE 18 — A-DCC gray-to-gray transition time performance. Average G-G is 8 msec and on + off time is 13 msec.

Advanced bus system interface (ABSI) LCD module

Brian H. Berkeley
Taesung Kim
Namsoo Kang
Marshall J. Bell
James Kozisek
Richard I. McCartney

Samsung Electronics Co.

Abstract — Samsung has successfully developed the world's first notebook panel based on Advanced Bus System Interface (ABSI) technology. ABSI is a new architecture which uses a point-to-point topology, serial gamma reference distribution, current-mode interface, and chip-on-glass (COG) technology to deliver a high-performance low-emission minimal-interconnect 8-bit-capable cost-effective LCD module in the smallest possible form factor. The first model is a 12.1-in. WXGA panel designed to work in an ultra-slim notebook application. This model combines ABSI technology with a-Si integrated gate drivers, resulting in the most advanced notebook panel manufactured to date.

Figure 13 shows a representative comparison of the wire and component count differences between a Reduced Swing Differential Signal (RSDS) and ABSI solution for a WXGA notebook PC. In both cases, a single timing controller (TCON) drives 10 column drivers (CDs). However, note the data line terminations and multitude of gamma references required for the conventional approach. ABSI is a point-to-point architecture, which does not require the multi-drop bus of RSDS;therefore the data connection consists of two single-ended lines per CD.

FIGURE 13 — Comparison of RSDS and ABSI WXGA solutions.

Peripheral circuit designs using low-temperature p-type poly-Si thin-film transistors

Woo-Jin Nam
Jae-Hoon Lee
Hye-Jin Lee
Hee-Sun Shin
Min-Koo Han

Seoul National University

Abstract — P-type low-temperature (450°C) polycrystalline-silicon thin-film-transistor circuits for peripheral driver integration in active-matrix displays are proposed and verified. A low-voltage (5 V) driven poly-Si scan driver is designed by employing a level shifter and shift register. A source driver for 6-bit digital interface is proposed, and the building blocks such as latch, DAC, and analog buffer are described. The latch samples and holds the digital bits (D and D¢) without an output voltage loss. A new source-follower-type analog buffer is developed and exhibits a small offset deviation regardless of the VTH variation of the buffer TFT. The simulation and measurement results ensure that the proposed circuits were successfully designed for p-type panel integration.

Figure 1(b) shows our proposed p-type driving scheme in the scan and source drivers for the digital interface. The scan driver is composed of a level shifter and a shift register. The external input clocks are 5 V and leveled up to 10 V by a level shifter. The shift register drives the output signals by single-phase 10-V clocks (ck/ckb), and they are leveled down to –8 V in order to address 0–5 V analog data from the source driver. The proposed level shifter as well as a shift register employs the bootstrap technique for the pull-down switching and requires only three supply voltages (10, 0, –8 V).

FIGURE 1 — P-type poly-Si TFT panel integration: (a) analog interface using the demultiplexing block drive and (b) proposed p-type integration for digital interface.

A new current-mirror pixel circuit employing poly-Si TFTs for active-matrix organic light-emitting-diode displays

Jae-Hoon Lee, Woo-Jin Nam,
Hee-Sun Shin, Min-Koo Han,
Yong-Min Ha, Hong-Seok Choi,
Chang-Hwan Lee
Soon Kwang Hong

Seoul National University

Abstract — A novel active-matrix organic light-emitting-diode (AMOLED) display employing a new current-mirror pixel circuit, which requires four poly-Si TFTs and one-capacitor and no additional signal lines, has been proposed and sucessfully fabricated. The experimental results show that a new current mirror can considerably compensate luminance non-uniformity and scale down a data current more than a conventional current-mirror circuit in order to reduce the pixel-charging time and increase the minimum data current. Compared with a conventional two-TFT pixel, the luminance non-uniformity induced by the grain boundaries of poly-Si TFTs can be decreased considerably from 41 to 9.1%.

A new current-mirror pixel circuit consisting of four TFTs and onecapacitor does not require any additional signal lines besides the scan and data signal lines, as shown in Fig. 1. Poly-Si TFTs in the proposed pixel design are recrystallized by an excimer-laser-annealing (ELA) line beam. When T3 and T4 have the same ELA conditions, the deviation of the electrical characteristics between T3 and T4 is negligible (VTH = VTH_T3 = VTH_T4, μ = μT3 = μT4).


FIGURE 1 — The serial-current-mirror pixel circuit and timing diagram, T3 and T4, are paired by a serial-mirror type.