A preview of the papers appearing in the July 2007 issue of the Journal of the SID. To obtain access to these articles on-line, please go to www.sid.org

Edited by Aris Silzars

Active-matrix organic light-emitting displays employing two thin-film-transistor a-Si:H pixels on flexible stainless-steel foil

Alex Z. Kattamis
Noel Giebink
I-Chun Cheng
Sigurd Wagner
Stephen R. Forrest
Yongtaek Hong
Vincent Cannella

Princeton University

Abstract — An active-matrix organic light-emitting diode (AMOLED) display driven by hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs) on flexible, stainless-steel foil was demonstrated. The 2-TFT voltage-programmed pixel circuits were fabricated using a standard a-Si:H process at maximum temperature of 280°C in a bottom-gate staggered source–drain geometry. The 70-ppi monochrome display consists of (48 x 4) x 48 subpixels each 92 x 369 μm, with an aperture ratio of 48%. The a-Si:H TFT pixel circuits drive top-emitting green electrophosphorescent OLEDs to a peak luminance of 2000 cd/m2.

Growing interest in flexible displays has extended to thin-film-transistor (TFT) backplanes on stainless-steel-foil substrates. Steel foils are attractive because of their tolerance to high-temperature processing, dimensional stability, chemical resistance, impermeability to moisture and other atmospheric contaminants, and a relatively low coefficient of thermal expansion. Here, we show that the a-Si:H TFTs width-to-length (W/L) ratio can be made large enough to deliver sufficient current to drive a top-emitting electrophosphorescent OLED.


FIGURE 1 — (a) Circuit schematic of a display subpixel. (b) Optical micrograph of one pixel with the TFTs and capacitance, Csindicated. The dashed-box outlines the location and size of the OLED. (c) Energy-level diagram of the OLED structure.

Effects of post-annealing on a-Si:H TFT characteristics fabricated on stainless-steel substrate

Chang-Wook Han
Chang-Dong Kim
In-Jae Chung

LG.Philips LCD R&D Center

Abstract — A 14.1-in.-diagonal backplane employing hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs) was fabricated on a flexible stainless-steel substrate. The TFTs exhibited a field-effect mobility of 0.54 cm2/V-sec, a threshold voltage of 1.0 V, and an off-current of 10–13 A. Most of the electrical characteristics were comparable to those of the TFTs fabricated on glass substrates. To increase the stability of a-Si:H TFTs fabricated on stainless-steel substrate, the specimens were thermally annealed at 230°C. The field-effect mobility was reduced to 71% of the initial value because of the strain of the released hydrogen atoms and residual compressive stress in a-Si:H TFT under thermal annealing at 230°C.

a-Si:H TFTs were fabricated on a 76-μm-thick SS substrate. A multi-barrier as an initial surface passivation was coated on the SS substrate in order to reduce the surface roughness of the SS substrate. The passivation layer also served as the mechanical bond between the TFT layers and the substrate. The root-mean-square (RMS) was improved from 110 to 3 nm after the passivation layer was coated on the SS sub-strate. The surface images measured by atomic force microscope (AFM) are shown in Fig. 1. The structure of the a-Si:H TFTs was that of an inverted staggered type which was made by a conventional five-photomask process.


FIGURE 1 — AFM images of a (a) bare surface and (b) passivated surface of the stainless-steel substrate.

Low-temperature amorphous-silicon backplane technology development for flexible displays in a manufacturing pilot-line environment

Gregory B. Raupp, Shawn M. O'Rourke,
Curt Moyer, Barry P. O'Brien,
Scott K. Ageno, Douglas E. Loy,
Edward J. Bawolek, David R. Allee,
Sameer M. Venugopal, Jann Kaminski,
Dirk Bottesch, Jeff Dailey,
Ke Long, Michael Marrs,
Nick R. Munizza, Hanna Haverinen,
Nicholas Colaneri

Arizona State University

Abstract — A low-temperature amorphous-silicon (a-Si:H) thin-film-transistor (TFT) backplane technology for high-information-content flexible displays has been developed. Backplanes were integrated with frontplane technologies to produce high-performance active-matrix reflective electrophoretic ink, reflective cholesteric liquid crystal, and emissive OLED flexible-display technology demonstrators (TDs). Backplanes up to 4 in. on the diagonal have been fabricated on a 6-in. wafer-scale pilot line. The critical steps in the evolution of backplane technology, from qualification of baseline low-temperature (180°C) a-Si:H process on the 6-in. line with rigid substrates to transferring the process to flexible plastic and flexible stainless-steel substrates, to form-factor scale-up of the TFT arrays, and finally manufacturing scale-up to a Gen 2 (370 x 470 mm) display-scale pilot line, will be reviewed.

In 2006, we completed a form-factor scale-up to a nominal 4-in.-diagonal 320 x 240 QVGA reflective backplane specifically designed to drive an electrophoretic-ink frontplane. The scale-up to QVGA from 64 x 64 represents an increase in pixel density from 82 to 105 ppi, and an increase in the number of TFTs per reflective array by nearly a factor of 20. Figure 11 shows the QVGA mask layout and a recently built high-quality EPD panel. The display exhibits good switching speed, contrast, and 4-bit gray scale.


FIGURE 11 — Mask layout with 4-in.-diagonal QVGA backplane (left) and assembled functional electrophoretic display panel (right).

Polysilicon-TFT technology on flexible metal foil for AMPLED displays

Ta-Ko Chuang
Matias Troccoli
Miltiadis Hatalis
Apostolos T. Voutsas

Lehigh University

Abstract — A top-emitting 230-dpi active-matrix polymer light-emitting diode (AMPLED) display, having a VGA format and a 3.3-in.-diagonal size, on a flexible stainless-steel-foil substrate is reported. The active-matrix array was fabricated with laser-crystallized polysilicon TFTs at a maximum process temperature of 700°C. The top-emitting PLED diodes were prepared by spin-casting organic light-emitting polymers. This work demonstrates the compatibility of polysilicon-TFT technology with flexible metal-foil substrates for active-matrix organic light-emitting-diode (AMOLED) display applications.

Stainless-steel foils offer very-high dimensional stability during the thermal-processing steps encountered in TFT fabrication. This allows for a minimum fabricated channel length of 1 μm (minimum feature size) as shown in Fig. 2. The technology presented here has resulted in TFTs with W/L =1 μm/1 μm, having a field-effect mobility of 358 cm2/V-sec (this value was achieved with SLS laser-annealing techniques and with grain sizes approaching that of channel lengths). A typical PMOS transistor used in the display presented here showed a mobility of 37(±4) cm2/V-sec, threshold voltage of –1.9(±0.6) V, and a sub-threshold slope of 1.16(±0.16) V/dec.


FIGURE 2 — Shown is a poly-Si TFT on metal foil of width and length of 1 μm.

Digital lithographic processing for large-area electronics

William S. Wong
Michael L. Chabinyc
Scott Limb
Steven E. Ready
Renè Lujan
Jurgen Daniel
Robert A. Street

Palo Alto Research Center

Abstract — A non-contact jet-printed mask-patterning process is described. By combining digital imaging with jet printing, digital lithography was used to pattern a-Si:H-based electronics on glass and plastic substrates in place of conventional photolithography. This digital lithographic process is capable of layer-to-layer registration of ±5 μm using electronic mask files that are directly jet printed onto a surface. A minimum feature size of 50 μm was used to create 180 x 180-element backplanes having 75-dpi resolution for display and image-sensor applications. By using a secondary mask process, the minimum feature size can be reduced down to ~15 μm for fabrication of short-channel thin-film transistors. The same process was also used to pattern black-matrix wells in fabricating color-filter top plates in LCD panels.

The process for patterning TFT devices involves several mask steps that require precise alignment after each deposition or etching step. The efficacy of the digital lithographic method by fabricating bottom-gate co-planar TFT arrays has been demonstrated. In this process, each mask layer defined the gate metal, active device island and source-drain metal contacts. First, a 100-nm-thick Cr film was deposited onto glass that was then patterned using a Kemamide-based wax ejected from a multi-ejector piezoelectric printhead. A 300-nm-thick Si3N4 layer followed by a 50-nm a-Si:H layer and a 100-nm N+–Si layer were deposited over the Cr gate creating the Si3N4/aSi:H/N+–Si (NSN+) device stack. Registration of the subsequent layers was accomplished by alignment to the gate layer whose image and alignment mark location was captured by a camera mounted on a microscope objective.


FIGURE 4 — Optical micrograph of a TFT array processed using digital lithographically patterned devices. The image is from a 128 ´ 128 element array.

100-MHz CMOS circuits directly fabricated on plastic using sequential laterally solidified silicon

Michael G. Kane
Lawrence Goodman
Arthur H. Firester
Paul C. van der Wilt
Alexander B. Limanov
James S. Im

Sarnoff Corp.

Abstract — CMOS TFT circuits were fabricated on plastic using sequential laterally solidified silicon combined with a low-temperature CMOS process. The unity-gain frequencies of the best of NMOS TFTs are greater than 250 MHz, and the CMOS ring oscillators operate at 100 MHz. To the best of the authors' knowledge, these are the highest-frequency circuits ever fabricated directly on plastic. This high-performance CMOS-on-plastic process can be applied to the fabrication of AMLCD integrated drivers and AMOLED pixels on plastic substrates.

To complement the sequential lateral solidification (SLS) crystallization process, a low-temperature CMOS fabrication process with a maximum process temperature of 300°C for compatibility with the polyimide substrates was developed. A schematic cross section of one of the completed TFTs is shown in Fig. 2. The substrate is a 10-μm-thick layer of spin-on polyimide on a 4-in.-diameter Si support wafer. Earlier material studies showed that the SLS crystallization process works successfully on free-standing polyimide films, but for the TFT and circuit results reported here the polyimide was applied to a support wafer so that all of the conventional TFT fabrication steps could be performed in a standard Si IC fabrication facility with automated wafer handling.


FIGURE 2 — Schematic cross-sectional drawing of an SLS TFT on a flexible substrate.

Flexible microelectronics becoming a reality with Suftla transfer technology

Mitsutoshi Miyasaka

Seiko Epson Corp.

Abstract — Suftla is a technology that is used to transfer polycrystalline silicon (polysilicon) thin-film-transistor (TFT) circuits from an original glass substrate to a plastic sheet. The electronic devices in the next generation will be thin, lightweight, and will handle huge amounts of data, yet consume less energy. Suftla technology, together with high-performance polysilicon TFTs, meets all these requirements. A variety of smart flexible electronic devices, such as thin paper-backsized displays and microprocessors, have been developed. Suftla will usher in a new era of life-enhancing flexible microelectronics.

The surface-free technology by laser annealing (Suftla) process consists of a first and a second transfer step. In the first transfer step, a sacrificial a-Si layer is formed on an original glass substrate. Poly-silicon TFT circuits [Fig. 1(a)] are then fabricated using a standard low-temperature process. After completion of polysilicon TFTs on the original glass substrate, a temporary glass substrate is glued onto the TFT surface using a temporary water-soluble adhesive [Fig. 1(b)]. Xenon chlorine (XeCl) excimer laser light (λ = 308 nm) is then irradiated onto the sacrificial a-Si layer from the back of the original glass substrate [Fig. 1(c)]. This process weakens the sticking force at the interface of the sacrificial a-Si layer, resulting in the easy separation of the TFT devices from the original glass substrate.

p43c_tif p43b_tif

FIGURE 1 — Suftla process.

All-additive ink-jet-printed display backplanes: Materials development and integration

Ana C. Arias
Jürgen Daniel
Brent Krusor
Steve Ready
Veronica Sholin
Robert Street

Palo Alto Research Center

Abstract — Methods used to deposit and integrate solution-processed materials to fabricate TFT backplanes by ink-jet printing are discussed. The materials studied allow the development of an all-additive process in which materials are deposited only where their functionality is required. The metal layer and semiconductor are printed, and the solution-processed dielectric is spin-coated. Silver nanoparticles are used as gate and data metals, the semiconductor used is a polythiophene derivative (PQT-12), and the gate dielectric is an epoxy-based photopolymer. The maximum processing temperature used is 150°C, making the process compatible with flexible substrates. The ION/IOFF ratio was found to be about 105–106, and TFT mobilities of 0.04 cm2/V-sec were obtained. The influence of surface treatments on the size and shape of printed features is presented. It is shown that coffee-stain effects can be controlled with ink formulation and that devices show the expected pixel response.

The control of the profile and thickness of printed lines allows pixel array design. Focusing on large-area electronics, display pixels with sizes varying from 500 x 500 μm to 1 x 1 mm were printed and tested. An example of a fully printed TFT array is given in Fig. 5. The pixel pitch is 680 x 680 μm, with line widths of ~70 μm and a space between printed features as small as 25 μm. Figure 5(a) is a photograph of the printed array on glass. A gate layer, shown in Fig. 5(b), is printed in two separate files because in this design the gateline is orthogonal to the gate electrode and pixel pads.


FIGURE 5 — Optical micrographs of (a) a fully printed TFT array, (b) gate layer, and (c) data layer.

Solution-processed organic TFT array for active-matrix LCDs on a plastic substrate

Kazumasa Nomoto
Nobuhide Yoneya
Nobukazu Hirai
Iwao Yagi
Noriyuki Kawashima
Makoto Noda
Jiro Kasahara

Sony Corp.

Abstract — Organic TFTs (OTFTs) have been developed with a novel solution-processed gate insulator of poly(4-vinylphenol) (PVP) with the addition of octadecyltrichloro-silane (OTS) and a solution-processed organo-silver electrode/wire to improve the performance of an OTFT and to make a high-throughput-manufacturing process possible. Solution-processed PVP has also been employed for a buffer layer on a plastic substrate. The OTFT backplane with these solution-based organic-material technologies has been successfully applied to drive a 2.5-in. QQVGA (160 x 120 pixels) AMLCD with a resolution of 79 dpi.

Figure 5 shows the structure of our pentacene OTFT-driven active-matrix TN-LCD. This is a conventional 1T-1C pixel with a pixel size of 320 x 320 μm. In this structure, every insulator layer is an organic material, which suppresses the formation of cracks frequently observed in an inorganic film on a plastic substrate due to thermo-mechanical stress between them. The backplane was processed on a 200-μm-thick 3-in. transparent PES substrate. Prior to device processing, the substrates were held to the Si carriers with a removable adhesive.


FIGURE 5 — (Left) Optical-micrograph image of a top view of a pixel. (Right) Schematic cross-section of OTFT-driven active-matrix TN-LCD developed.

Flexible color LCD panel driven by low-voltage-operation organic TFT

Yoshihide Fujisaki
Hiroto Sato
Toshihiro Yamamoto
Hideo Fujikake
Shizuo Tokito
Taiichiro Kurita

NHK Science & Technical Research Laboratories

Abstract — A flexible color LCD panel driven by organic TFTs (OTFTs) was successfully demonstrated. A pentacene OTFT with an anodized Ta2O5 gate insulator, which can be operated at low voltage, was developed. In order to improve the electrical performance of the OTFT, the gate insulator was surface treated by processes such as O2 plasma, UV light irradiation, and hexamethyldisilane treatments. The fabricated OTFT exhibited a mobility of 0.3 cm2/V-sec and a current on/off ratio of 107 with a low operating drain voltage of –5 V. A fast-response-time flexible ferroelectric LCD, which contains polymer networks and walls, was integrated with the OTFTs by using a lamination and a printing technique. As a result, color images were achieved on the fabricated panel by using a field-sequential-color method at a low driving voltage of less than 15 Vpp.

The schematic cross section of a fabricated pixel is illustrated in Fig. 2. The drain electrode of the OTFT is connected to a pixel pad of 100-nm-thick indium tin oxide (ITO), which was deposited by using facing target sputter at room temperature and patterned by a liftoff method before the formation of the source/drain electrode. To prevent degradation of the OTFT during the process, a double passivation layer consisting of water-based polyvinylalchol (PVA) and photo-curable acrylic film (PAF), is coated over the OTFT array.


FIGURE 2 — Schematic cross section of a fabricated pixel.

Confined-error-diffusion algorithm for flat-panel display

Jun-Hak Lee
Takahiko Horiuchi
Ryoichi Saito

Chiba University

Abstract — The reduction of a structural pattern at specific gray levels caused by digital halftone methods is the subject of this paper. This problem is more severe in some flat-panel displays because their black levels typically are brighter than other display blocks. A patented halftone algorithm, confined error diffusion (CED), that confines the error-carry within the dither mask is described and extended. First, the CED algorithm that dynamically applies random error diffusion or the ordered-dither method, depending upon image content, is described in detail. Finally, an advanced CED algorithm for improving the gradation characteristics of the CED algorithm has been proposed. The performance of the proposed algorithms is compared to the experimental results for natural test images. In order to verify the halftone quality, a structural similarity measure for color images by taking into account the interrelation between color channels is proposed, and the results based on the proposed method, the color similarity measure method, is given.

The results of various types of halftones using Floyd-Steinberg error diffusion (raster scan), Shiau Fan error diffusion, 6-bit ordered dither, the CED algorithm, and the ACED algorithm, with the source of the "gradation ramp" image in Fig. 20, were compared. The size of the gradation-ramp image is 256 x 128 pixels and the image has a structure that increases or decreases 1 gray level/4 pixels. In (e) and (f) of Fig. 20, the gradation characteristic of the CED algorithm is improved by using the ACED algorithm. The flat area of the CED algorithm is decreased in (f) of Fig. 20.


FIGURE 20 — Result for gradation ramp (one-frame image).

Gradually tapered light pipes for illumination of LED projectors

Hüseyin Murat
An Gielen
Herbert De Smet

Ghent University

Abstract — LEDs are totally different from classical light sources: they have a different shape, radiation pattern, driving requirements, etc. Therefore, the illumination engine, which determines the brightness and uniformity of the system, has to be redesigned for LED-based projectors. A compact illumination system based on gradually tapered light pipes (GTLP) will be presented. The GTLP collects, reshapes, and uniformizes the light flux from the LED to illuminate the light-valve uniformly. The design and the simulations have been completed. The result is a uniformly illuminated rectangular beam at the end of the pipe with an efficiency of 81.1%. Afterwards, the light pipe was fabricated, and the experimentally measured efficiency is 76.9%, which demonstrates a successful manufacturing process. Finally, two recycling techniques to enhance the brightness have been applied and these enhancements were experimentally observed.

To make the projector more compact and efficient, the collection lens and the integrator pipe was combined in one component based on the tapered light pipe (TLP) principle. A TLP is a component that acts as a collector and an integrator and at the same time adapts the radiation pattern into the desired acceptance angle. The light from the LED will be directly and entirely coupled into the TLP and will propagate through the pipe. Because of its tapered sides, each time a ray crosses the side it will be reflected under a smaller angle.


FIGURE 7 — (b) Polished GTLP + LED setup.

Transflective twisted-nematic liquid-crystal display with double twisted-nematic cell and twisted liquid-crystal retarder

Hin Yu Mak
Vladimir G. Chigrinov
Hoi-Sing Kwok

Hong Kong University ofScience and Technology

Abstract — Two configurations, (i) a double-cell-gap twisted nematic (DTN) liquid-crystal display (LCD) and (ii) a single-cell-gap twisted-nematic (TN) liquid-crystal display (LCD) using a twisted LC retarder, were optimized for transflective liquid-crystal displays. For the DTN configuration, both the single-cell-gap approach and the double-cell-gap approach were considered. The optimized configurations exhibit a high contrast ratio, wide viewing angles, and achromatic (black/white) switching in both the transmissive and reflective modes. They are easy to fabricate and also possess a perfect dark state. Both are suitable for high-quality transflective TFT-LCDs

Figure 7 shows the configuration of the transflective TN cell with a twisted LC retarder. Although using a double-cell configuration could provide better optical performance, it will also increase the overall thickness of the LCD. In order to solve this problem, a twisted LC retarder is used to replace the passive LC layer in the DTN configuration. Only the single-cell-gap approach can be considered in this case because it is not easy to produce a patterned twisted LC retarder.


FIGURE 7 — Configuration of the transflective TN cell with a twisted LC retarder.